6T SRAM at 45nm CMOS technology for low power optimization
نویسنده
چکیده
SRAM is designed to provide an interface with CPU and to replace DRAMs in systems that require very low power consumption. Low power SRAM design is crucial since it takes a large fraction of total power and die area in high performance processors. A SRAM cell must meet the requirements for the operation in submicron/nano ranges. 8T SRAM is traditionally concerned as a more reliable memory cell, but we have managed to design 6T SRAM which executes read operation with an acceptable reliability; read being the most vulnerable operation of conventional 6T SRAM cell. Also, our 6T SRAM cell has 31 % smaller area and smaller power consumption. A 6T SRAM cell at 45 nm feature size in CMOS is proposed to accomplish low power memory operation. This paper presents design of 6T SRAM cell considering low power consumption and the comparison of 6T SRAM cell with 8T SRAM cell.
منابع مشابه
An Analysis of Power and Stability in 6T, NC, Asymmetric, PP, and P3SRAM Bit-Cells Topologies in 45nm CMOS Technology
In modern digital architectures, more and more emphasis has been laid on increasing the number of SRAMs in a SoC. However, with the increase in the number of SRAMs, the power requirement also increases, which is not desired. This calls for an urgent need for an SRAM with low dynamic and static power consumption and stability at the same time. The design and simulation work for 6T-SRAM, NC-SRAM,...
متن کاملLow Leakage Asynchronous PP based Single Ended 8T SRAM bit-cell at 45nm CMOS Technology
Low power SRAM memory designs has become challenging for portable device applications. Semiconductor/ VLSI industry growth has exponentially demanding low leakage power SRAM designs for high performance chips and microprocessors. To get optimized standard cell memory design for battery operated devices at deep sub micron CMOS technology, a low leakage Asynchronous 8T SRAM is proposed. In this p...
متن کاملCell Stability Analysis of Conventional 6t Dynamic 8t Sram Cell in 45nm Technology
A SRAM cell must meet requirements for operation in submicron/nano ranges. The scaling of CMOS technology has significant impact on SRAM cell -random fluctuation of electrical characteristics and substantial leakage current. In this paper we present dynamic column based power supply 8T SRAM cell and comparing the proposed SRAM cell with respect to conventional SRAM 6T in various aspects. To ver...
متن کاملLow Power and Improved Read Stability Cache Design in 45nm Technology
–Cache is fastest memory which is played vital role in the present trend.Cache is achieved by SRAM. The scaling of CMOS technology has significant impact on SRAM cell -random fluctuation of electrical characteristics and substantial leakage current. In this paper we proposed dynamic column based power supply 8T SRAM cell to improve the read stability and low leakage. In this paper we compare th...
متن کاملAverage and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm, and 45nm CMOS Technology for a High Speed SRAMs
A lot of consideration has been given to problems arising due to power dissipation. Different ideas have been proposed by many researchers from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between the power, delay and area. This is why; the designers are required to choose appropriate techniques that satisfy application and product...
متن کامل